When a clock signal is transmitted from a transmitting side to a receiving side in an electronic device, an electromagnetic wave is produced by the clock signal during propagation in a transmission line. When the electromagnetic wave has a high intensity, the electromagnetic wave may act as EMI (electro-magnetic interference) noise. A wiring configuration in which a damping resistor or an EMI filter is interposed into the clock transmitting side is generally employed for the purpose of reducing EMI noise.
FIG. 1 illustrates a configuration in which a damping resistor is interposed into a single clock wiring, and a clock signal is transmitted in a single phase. The configuration in FIG. 1 encounters the following problems. Firstly, the emission of the electromagnetic wave from the wiring increases in proportion to an increase in the wiring length. Furthermore, as the wiring length increases, the wiring capacity increases and the amplitude of the clock signal at the signal receiving end decreases. Although electromagnetic wave emission from the wiring and the effect of signal reflection can be reduced by increasing the damping resistor or the EMI filter, the amplitude of the clock signal at the signal receiving end decreases.
If the amplitude of the clock signal at the signal receiving end decreases, the signal voltage threshold required at the signal receiving side may not be reached, and therefore there is a risk that the clock signal will not be detected. Furthermore, there is the risk of increased jitter in the received clock signal as a result of the risk of an increase in the rise time and the fall time of the signal. FIG. 2 illustrates a configuration of transmitting a clock signal as a differential signal after damping by a damping resistor. The use of the differential configuration illustrated in FIG. 2 enables the following advantages in relation to the problems associated with the single-phase configuration illustrated in FIG. 1. Firstly, since the clock signal is transmitted in the form of a differential signal, electromagnetic wave emissions can be suppressed due to the fact that signals of opposite polarity cancel out mutual electromagnetic fields. Secondly, a clock signal transmitted in the form of a differential signal is strongly resistant to external noise, and the clock can be detected accurately by the signal receiving end even when the signal amplitude is reduced by long-range transmission of the clock signal.
The configuration illustrated in FIG. 2 uses LVDS (low voltage differential signaling) for example as the differential signal system. LVDS is a normalized standard that realizes a comparatively high data rate with low power consumption. The configuration illustrated in FIG. 2 disposes an LVDS transmitter 10 and an LVDS receiver 11 respectively at the transmitting end and the receiving end, and uses a differential 100 ohm wiring 12 to connect the LVDS transmitter 10 and the LVDS receiver 11. This configuration results in a considerable cost increase in comparison to the configuration in FIG. 1 due to the addition of components (LVDS transmitter and receiver) to both the transmitting end and the receiving end. Furthermore, the requirement for the wiring 12 between the LVDS transmitter 10 and the LVDS receiver 11 to be designated differential 100 ohm wiring has the effect of limiting the degree of freedom in respect of the wiring layout.
Transmission of the clock signal in single phase is preferred in view of the degree of freedom in the wiring layout, and cost. However, single-phase clock transmission requires a configuration that enables accurate detection of the clock signal at the receiving end even when EMI noise is sufficiently reduced by a damping resistor.
Several publications disclose a configuration in which a clock signal is transmitted in single phase, and the clock signal is received by an LVDS receiver (for example, Non-patent Literatures 1 and 2). The configuration disclosed in these publications applies a clock signal, that is regulated to a suitable amplitude by a series of resistors, to a first end of an LVDS receiver, and applies a reference voltage, that is produced by the dividing of the power source voltage with the series of resistors, to the second end of the LVDS receiver. The effect of power source noise on the reference voltage is eliminated by interposing a capacitor between the LVDS receiver and the GND of the second end. This configuration enables detection of the clock signal by comparing the fixed reference voltage with the voltage of the clock signal that includes a DC component. However, when there is a distortion in the amplitude of the clock signal or a deviation in the DC component as a result of the effect of the wiring for example, the relationship between the reference voltage and the received clock signal voltage diverges from an ideal voltage relationship, and suitable signal detection is not enabled.